1. Field of the Invention
This invention relates to a method for fabricating a stacked chip package, and more specifically to packaging semiconductor chips on a substrate in a stacking arrangement.
2. Description of the Related Art
FIG. 1 depicts a conventional stacked chip package 100 comprising two chips 110, 130 stacked each other. The chip 110 is attached onto the upper surface of a substrate 150 through an adhesive layer 112. An adhesive layer 132 is interposed between the chips 110, 130. The chips 110, 130 are respectively connected to chip connection pads 152 on the upper surface of the substrate 150 through bonding wires 114, 134. The lower surface of the substrate 150 is provided with a plurality of solder pads electrically connected to the chip connection pads 152 on the upper surface of the substrate 150. Each solder pad 154 is provided with a solder ball 156 for making external electrical connection. A package body 160 encapsulates the chips 110, 130, the bonding wires 114, 134 and a portion of the upper of the substrate 150. Typically, the adhesive layers 112, 132 are made of thermosetting epoxy material.
Referring to FIG. 2, in mass production of the stacked chip package 100, it is desirable to integrally form a plurality of substrates in a strip 170 having alignment holes (not shown) so as to facilitate the automation packaging process (including encapsulation). Normally, the semiconductor chip is formed of microcrystalline silicon with a coefficient of thermal expansion (CTE) of 3-5 ppmxc2x0 C.xe2x88x921. The strip 170 is usually formed of polymer impregnated fiberglass having a coefficient of thermal expansion of 25-40 ppmxc2x0 C.xe2x88x921 and the thickness of the strip is less than 0.36 mm. Since there is a significant difference between the semiconductor chip 110 and the strip 170 in CTE and the strip 170 is rather thin, the semiconductor chip 110 and the strip 170 expand and contract in different amounts along with temperature fluctuations during the curing process of the adhesive layer 112 thereby causing the semiconductor chip 110 and the substrate 150 to warp. The curing process of the adhesive layer (such as 8355F epoxy adhesive available from ABLESTICK LABORATORY) typically requires one hour of precure at 110xc2x0 C. and two hours of postcure at 175xc2x0 C. The higher curing temperature and longer curing time are employed, the greater warpage the semiconductor chip 110 and the substrate 150 will produce.
Referring to FIG. 2, the warped substrate 150 and semiconductor chip 110 will result in adverse influences on the chip 100 itself and the subsequent manufacturing process. For example, the warped substrate 150 and semiconductor chip 110 may bring about positioning errors during dispensing the adhesive layer 132, such that the epoxy adhesive can not be dispensed in precise amounts and to correct positions on the chip 110. This makes the epoxy adhesive easy to bleed to contaminate the bonding pads 110a thereby adversely affecting the wire bonding process. Furthermore, this may cause the bonding layer on the chip 110 formed from the epoxy adhesive to have incomplete filling problem thereby adversely affecting the bonding quality between the semiconductor chip 110 and chip 130.
It is noted that the adhesive layers 112, 132 of the stacked chip package 100 must be cured separately. This prolongs the cycle time for manufacturing the package 100 thereby increasing the production cost.
Curing temperature of the adhesive layers 112, 132 depends on the materials used in the adhesive layers 112, 132; typically, it is higher than the maximum exothermic temperature of the adhesive layers 112, 132. The maximum exothermic temperature of the adhesive layers 112, 132 can be calculated from the heat of cure curve for the adhesive layers 112, 132 detected by Differential Scanning Calorimeter (DSC).
It is a primary object of the present invention to provide a method for fabricating a stacked chip package wherein the curing process and materials of adhesive layers are optimized to minimize the warpage of the substrate and the chip as well as reduce the cycle time for the assembly process.
The method for fabricating a stacked chip package in accordance with the present invention comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer, the substrate being provided with a structure for making external electrical connection; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to the structure for making external electrical connection; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate.
According to one aspect of the present invention, during the step of partial curing, the first adhesive layer is heated to a temperature at which it gels but does not harden (the gelling temperature and time are material dependent, typically 30 minutes at 110xc2x0 C.). Thus, during the step (b), the heating temperature and time for the first chip and the substrate are reduced such that the first chip and the substrate dose not experience much thermal stress. Therefore, the resulting warpage of the first chip and the substrate is minimized thereby assuring the proceeding of subsequent processes such as the dispensing of the second adhesive layer during step (c). Besides, since the first and the second adhesive layers are cured in one single step, the cycle time for the assemble process illustrated in the present invention is reduced thereby cutting down the production cost.
According to another aspect of the present invention, it is preferable to choose the proper material of each of the adhesive layers such that the maximum exothermic temperature of the second adhesive layer is lower than that of the first adhesive layer. This makes the second adhesive layer cure at a lower temperature during step (d) thereby forming a protection layer on the first chip. Therefore, during the curing process of the first adhesive, the cured second adhesive layer can help the first chip to resist stresses created in the curing process, thereby reducing the problem of die cracking.